SC740 SEMINAR REPORT 04 for Frederick L. Jones

PRESENTER: Shahram Rahimi

TOPIC: Combination of a Processor with a Reconfigurable Coprocessor

OVERVIEW

Shahram Rahimi started his seminar with a description of ASAL Architecture. ASAL Architecture combines a MC68030 Motorola processor with a reconfigurable coprocessor. The reconfigurable coprocessor consists of basic hardware building blocks like control blocks, logic blocks and memory buses.

An individual configuration consists of some of these basic hardware building blocks. Some applications may need more multibit adders, multibit shifters and other such multibit functions than others. ASAL Architecture allows the user to program the hardware configuration to be used for any application.

RECONFIGURABLE HARDWARE

Shahram Rahimi started his seminar with a statement that reconfigurable hardware can be used to build integrated circuits (IC’s). This I assume is because a particular IC logic design requirement may require several iterative refinements before it is finalized. Therefore, having the capability to program the hardware configuration at the logic module block level provides the capability of each user to optimize the hardware.

Shahram Rahimi also compared the particular reconfigurable hardware that he is working on (i.e., ASAL Architecture) with other reconfigurable hardware such as Field Programmable Gate Array (FPGA) Architecture. As noted by Shahram Rahimi, FPGA technology is based on static RAM building blocks. The obstacles noted by Shahram Rahimi to the use of FPGA technology is that the cache memory is too small to encode entire programs, there is too much swapping of code out between cache memory and regular memory, and FPGA technology is not as efficient as the hardware.

ASAL ARCHITECTURE

As described by Shahram Rahimi, ASAL Architecture is a combination of a MC68030 Motorola processor with a reconfigurable coprocessor. ASAL Architecture consists of the following: (1) a standard processor, (2) cache memory (3) regular memory with multiple memory busses and (4) the reconfigurable array coprocessor.

The reconfigurable array coprocessor consists of basic hardware building blocks like control blocks, logic blocks, and memory buses. Control blocks control array memory access. The logic blocks allow the creation of multibit functions such as adders and shifters. There are nineteen sets of hardware building blocks per row. Vertical and horizontal wires interconnect the blocks.

An individual configuration consists of some of these basic hardware building blocks. These basic hardware building blocks are reconfigured through the use of modified Motorola assembler instructions that store configuration data in these blocks. Up to 64 bits of configuration data can be stored in each block.

THE SOFTWARE ENVIRONMENT

As described by Shahram Rahimi, ASAL Architecture allows the user to program the hardware configuration to be used for any application. The Configurator program generates a text file (e.g., config.txt ) that is included in a C program in an include statement. A standard C preprocessor reads in the ASAL assembler, and a standard C compiler generates the object deck. The linking and execution of the object deck loads the configuration data into the hardware building blocks.

SUMMARY AND CONCLUSIONS

As described by Shahram Rahimi, ASAL Architecture combines a MC68030 Motorola processor with a reconfigurable coprocessor. The reconfigurable coprocessor consists of basic hardware building blocks like control blocks, logic blocks and memory buses. An individual configuration consists of some of these basic hardware building blocks. ASAL Architecture allows the user to program the hardware configuration to be used for any application.

Shahram Rahimi concluded his seminar by restating that ASAL like Architecture is better FPGA only machines and by adding one more advantage of ASAL Architecture over other Architectures. Shahram Rahimi stated that ASAL Architecture would have a substantial advantage over standard RISC processors.

I wholeheartedly agree with Shahram Rahimi, since RISC processors are by definition specialized processors whose assembly language instructions were included in a reduced instruction set after a prespecified application was optimized. RISC Architecture machines are designed after hardware instrumentation data has been collected from predefined benchmark workloads run on an existing architecture. Thus ASAL Architecture processors have an advantage over standard RISC processors, since they are not locked into being optimized for only one application.